Configurable or programmable logic devices are a general class of electronic devices that can be easily configured to perform a desired logic operation or calculation. Mask Programmed Gate Arrays (MPGA) offer density and performance. Poor turn around time coupled with only one-time configurability tend to advocate against MPGA usage. Field Programmable Gate Arrays (FPGA) offer lower levels of integration but are reconfigurable, i.e., the same FPGA may be programmed many times to perform different logic operations. Most importantly, the FPGAs can be programmed to create gate array prototypes instantaneously, allowing complete dynamic reconfigurability, something which MPGAs can not provide.
System designers commonly use configurable logic devices to test logic designs prior to manufacture or fabrication in an effort to expose design flaws. Usually, these tests take the form of emulations in which a configurable logic device models the logic design, such as a microprocessor, in order to confirm the proper operation of the logic design along with possibly its compatibility with a system in which it is intended to operate.
In the case of testing a proposed microprocessor logic design, a netlist describing the internal architecture of the microprocessor is compiled for and then loaded into a particular configurable logic device by some type of configuring device such as a host workstation. If the configurable logic device is a single or array of FPGAs, the loading step is as easy as down-loading a file describing the compiled netlist to the FPGAs using the host workstation or other computer. The programmed configurable logic device is then tested in the environment of a motherboard by confirming that its response to inputs agrees with the design criteria for the proposed microprocessor.
Alternatively, a configurable logic device also finds application as hardware accelerators for simulators. Rather than testing a logic design by programming a configurable device to "behave" as the logic device in the intended environment for the logic design, e.g., the motherboard, a simulation involves modeling the logic design and its environment on a workstation. In this context, the configurable logic device functions as a hardware accelerator that performs gate evaluations for portions of the model in order to relieve the workstation of this task and thereby decreases the time required for the simulation.
Recently, most of the attention in complex logic design emulation/simulation has been directed toward FPGAs. The lower integration of the FPGAs has been overcome by forming heterogeneous networks of special purpose FPGA processors connected to exchange signals via some type of interconnect. The network of the FPGAs is heterogeneous not necessarily in the sense that it is composed of an array of different devices, but that the devices have been individually configured to cooperatively execute different sections, or partitions, of the overall logic design. These networks rely on static routing at compile-time to organize the propagation of logic signals through the FPGA network. Static refers to the fact that all data or logic signal movement can be determined and optimized during compiling.
More recently, networks implementing time division multiplexing have been proposed and constructed. These emulators overcome the inherent pin limitations associated with each FPGA and the bandwidth/speed limitations of buses by configuring the FPGA to stack logic signals in time and then transmit the signals on successive clock pulses to a destination FPGA, possibly routing the signals through an intermediate FPGA or through networks, where the signals are then demultiplexed. See U.S. Pat. application Ser. No. 08/042,151, filed on Apr. 1, 1993 by the present inventors and incorporated herein by this reference.